One major concern in IC design is that timing misalignments could result in race conditions. A race condition or race hazard is a flaw in an electronic system or process whereby an output and/or result of the system or process is unexpectedly and critically dependent on the sequence or timing of other events. Data should generally arrive at a component (e.g., latch or flip-flop) a prescribed amount of time before a clock signal (e.g., setup time) and data should be stable for a prescribed amount of time until new data arrives (e.g., hold time). If the data and clock signals are not synchronized in this manner, unpredictable and undesirable results could occur.
A common metric utilized in timing analysis is “slack,” which is typically defined as the difference between the expected time of data arrival and the actual time of data arrival. Negative slack means that the data is delayed, so the clock speed must be decreased accordingly. Conversely, positive slack indicates that the data is early, so the clock speed could be increased. If a manufactured IC has any negative slacks, it is often considered to be defective and is discarded.
Manufactured ICs are subject to wide performance distributions due to manufacturing process variations, and the like, which can cause timing misalignments, including negative slacks. Accordingly, it is necessary to test the ICs prior to deployment (e.g., shipping to a customer or using in a product). Typical methods of testing ICs include an at-speed structure test (ASST) and functional testing. However, it is often desirable to perform an initial screening of ICs even before the final testing of the IC. This screening, commonly known as IC disposition, allows for the discovery of ICs which would otherwise be incapable of passing the next stages of testing, thus allowing for these ICs to be identified and discarded earlier in the testing process.